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this document is a general product description and is subject to change without notice. hynix semiconductor does not assume any responsibility for use of circuits described. no patent licenses are implied. rev.0 7 / aug . 2001 hynix semiconductor HY62UF16201A series 128 kx16bit full cmos sram document title 128k x16 bit 3.0v super low power full cmos slow sram revision history revision no history draft date remark 05 divide output load into two factors dec.10. 2000 final - tclz,tolz,tblz,tchz,tohz,tbhz,twhz,tow - others add the marking information 06 co rrect the pkg dimension(e1) aug. 01. 2001 add the dimension and the marking information of the 6x8 pkg size 07 separate the part number(HY62UF16201Af 1 ) for the 6x8 pkg aug. 3 1. 2001 size from the 7x8 pkg size(HY62UF16201Af)
HY62UF16201A series rev.0 7 / aug . 2001 2 descri ption the HY62UF16201A is a high speed, super low power and 2 mbit full cmos sram organized as 131 , 072 words by 16bits. the HY62UF16201A uses high performance full cmos process technology and is designed for high speed and low power circuit technology. it is particularly well - suited for the high density low power system application. this device has a data retention mode that guarantees data to remain valid at a minimum power supply voltage of 1. 2 v. features fully static operation and tri - state outpu t ttl compatible inputs and outputs battery backup(ll/sl - part) - . 1. 2 v(min) data retention standard pin configuration - . 48 - fbga product voltage speed operation standby current(ua) temperature no. (v) (ns) current /icc (ma) ll sl ( c ) HY62UF16201A 2.7~3.3 55/70/85 /100 3 1 0 2 0~70 HY62UF16201A - i 2.7~3.3 55/70/85/100 3 1 0 2 - 40~85( i ) note s : 1. blank : commercial , i : industrial 2. current value is max. pin connection block diagram /lb io9 io10 /oe a0 a1 a2 nc /ub a3 a4 /cs io1 io11 a5 a6 io2 io3 vss io12 nc a7 io4 vcc vcc io13 nc a16 io5 vss io15 io14 a14 a15 io6 io7 io16 nc a12 a13 /we io8 nc a8 a9 a10 a11 nc 48 - fbga(top view) pin description pin name pin fun c tion pin name pin fun c tion /cs chip select i/o1~i/o16 data input s / output s /we write enable a0~a16 address input s /oe output enable vcc power( 2.7v~3.3v ) /lb low er byte control(i/o1~i/o8) vss ground /ub upper byte control(i/o9~i/o16) nc no connection memory array 128k x 16 row decoder sense amp write driver data i/o buff er i/o1 i/o16 columndecoder control logic add input buffer a0 a16 /cs /oe /lb /ub /we
HY62UF16201A series rev.0 7 / aug . 2001 2 ordering information part no. speed power temp. package HY62UF16201All f 55/70/85/100 ll - part fbga(7mm x 8mm) HY62UF16201All f - i 55/70/85/100 ll - part i fbga(7mm x 8mm) HY62UF16201A s l f 55/70/85/100 s l - part fbga(7mm x 8mm) HY62UF16201Asl f - i 55/70/85/100 sl - part i fbga(7mm x 8mm) HY62UF16201All f1 55/70/85/100 ll - part fbga(6mm x 8mm) HY62UF16201All f1 - i 55/70/85/100 ll - part i fbga(6mm x 8mm) hy62 uf16201a s l f1 55/70/85/100 s l - part fbga(6mm x 8mm) HY62UF16201Asl f1 - i 55/70/85/100 sl - part i fbga(6mm x 8mm) note : 1. blank : commercial, i : industrial absolute maximum ratings (1) symbol parameter rating unit remark v in, v out input/output volt age - 0.2 to 3.6 v vcc power supply - 0.2 to 4. 6 v t a operating temperature 0 to 70 c HY62UF16201A - 40 to 85 c HY62UF16201A - i t stg storage temperature - 55 to 150 c p d power dissipation 1.0 w t solder ball soldering temperature & time 260 10 c sec note 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is stress rating only and the functional operation of the device under these or any other conditions above those indi cated in the operation of this specification is not implied. exposure to the absolute maximum rating conditions for extended period may affect reliability. truth table i/o /cs /we /oe /lb /ub mode i/o1~i/o8 i/o9~i/o16 power h x x x x des el ected hi gh - z hi gh - z standby x x x h h deselected hi gh - z hi gh - z standby l h h l x output disabled hi gh - z hi gh - z active l h h x l output disabled hi gh - z hi gh - z active l h l l h read d out hi gh - z active h l hi gh - z d out l l d out d out l l x l h write d in hi gh - z active h l hi gh - z d in l l d in d in note : 1. h=v ih , l=v il , x=don't care 2. ub, lb(upper, lower byte enable) these active low inputs allow individual bytes to be written or read. when lb is low, data is written or read t o the lower byte, i/o 1 - i/o 8. when ub is low, data is written or read to the upper byte, i/o 9 - i/o 16.
HY62UF16201A series rev.0 7 / aug . 2001 3 recommended dc operating condition symbol parameter min. typ. max. unit vcc supply voltage 2.7 3.0 3.3 v vss ground 0 0 0 v v ih input high voltage 2.2 - vcc+0. 3 v v il input low voltage - 0. 3 (1) - 0. 6 v note : 1. vil = - 1.5v for pulse width less than 30ns dc electrical characteristics t a = 0 c to 70 c / - 40 c to 85 c ( i ) sym bol parameter test condition min . typ . max . unit i li input lea kage current vss < v in < vcc - 1 - 1 ua i lo output leakage current vss < v out < vcc, /cs = v ih or / oe = v ih or /we = v il , / ub = /lb = v ih - 1 - 1 ua icc operating power supply current /cs = v il , v in = v ih or v il , i i/o = 0ma - - 3 ma cycle time = min.100% duty, /cs = v i l, v in = v ih or v il , i i/o = 0ma - - 45 m a i cc1 average operati ng current cycle time = 1us, /cs < 0.2 v, v in <0.2v, i i/o = 0ma 5 m a i sb standby current (ttl input) /cs = v ih or /ub & /lb = v ih , v in = v ih or v il - - 0.3 ma sl - - 2 ua i sb1 standby c urrent (cmos input) /cs > vcc - 0.2v or /ub = /lb > vcc - 0.2v, v in > vcc - 0.2v or ll - 0.5 1 0 ua v in < vss + 0.2v v ol output low voltage i ol = 2.1 ma - - 0.4 v v oh output high voltage i oh = - 1.0 ma 2. 4 - - v notes : 1. typical values are at vcc = 3.0 v, t a = 25 c 2. typical values are sampled and not 100% tested capacitance (temp = 25 c , f= 1.0mhz) symbol parameter condition max. unit c in input capacitance(add, /cs, /we, /oe) v in = 0v 8 pf c out output capacitance( i/o) v i/o = 0v 10 pf note : 1. these parameters are sampled and not 100% tested
HY62UF16201A series rev.0 7 / aug . 2001 4 ac characteristics t a =0 c to 70 c / - 40 c to 85 c ( i ),unless otherwise specified - 55 - 70 - 85 - 10 min ma x min max min max min max read cycle 1 t rc read cycle time 55 - 70 - 85 - 100 - ns 2 taa address access time - 55 - 70 - 85 - 100 ns 3 tacs chip select access time - 55 - 70 - 85 - 100 ns 4 toe output enable to output valid - 30 - 35 - 40 - 50 ns 5 tba /lb, /ub access time - 5 5 - 7 0 - 85 - 100 ns 6 tclz chip select to output in low z 10 - 10 - 10 - 20 - ns 7 tolz output enable to output in low z 5 - 5 - 5 - 5 - ns 8 tblz /lb, /ub enable to output in low z 5 - 5 - 5 - 5 - ns 9 tchz chip deselection to output in high z 0 30 0 30 0 30 0 30 ns 10 tohz out disable to output in high z 0 30 0 30 0 30 0 30 ns 11 tbhz /lb, /ub disable to output in high z 0 30 0 30 0 30 0 30 ns 12 toh output hold from address change 10 - 10 - 10 - 15 - ns write cycle 13 twc write cycle time 55 - 70 - 85 - 100 - ns 14 tcw chip selection to end of write 50 - 60 - 70 - 80 - ns 15 taw address valid to end of write 50 - 60 - 70 - 80 - ns 16 tbw /lb, /ub valid to end of write 50 - 60 - 70 - 80 - ns 17 tas address set - up time 0 - 0 - 0 - 0 - ns 18 twp wri te pulse width 45 - 50 - 55 - 75 - ns 19 twr write recovery time 0 - 0 - 0 - 0 - ns 20 twhz write to output in high z 0 20 0 25 0 30 0 35 ns 21 tdw data to write time overlap 25 - 30 - 35 - 45 - ns 22 tdh data hold from write time 0 - 0 - 0 - 0 - ns 23 tow output active from end of write 5 - 5 - 5 - 10 - ns ac test conditions t a = 0 c to 70 c / - 40 c to 85 c ( i ),unless otherwise specified parameter value input pulse level 0.4v to 2.2v input rise and fall time 5ns input and output timing referen ce level 1.5v tclz,tolz,tblz,tchz,tohz,tbhz,twhz,tow cl = 5pf + 1ttl load output load others cl = 30pf + 1ttl load ac test loads d out 1728 ohm cl(1) 1029 ohm v tm = 2.8v note : 1 . including jig and scope capacitance parameter uni t symbol #
HY62UF16201A series rev.0 7 / aug . 2001 5 timing diagram read c ycle 1( n ote 1,4 ) read cycle 2(note 2 , 3 ,4) addr data out trc taa data valid previous data toh toh read cycle 3(note 1,2 ,4) /cs /ub, /lb data out tacs data valid tclz(3) tchz(3) notes: a r ead occurs during the overlap of a low /oe, a high /we, a low /cs1 and low /ub and / or /lb . 2. /oe = v il 3. transition is measured + 200mv from steady state voltage. this parameter is sampled and not 100% tested. 4. /cs in high for the standby, low for active /ub and /lb in high for the standby, low for active addr trc / cs taa tacs toh data valid high - z data out / ub ,/ lb / oe tba toe tclz (3) tblz (3) t olz (3) t chz (3) t bhz (3) tohz (3)
HY62UF16201A series rev.0 7 / aug . 2001 6 write cycle 1 (1,4,8) (/we controlled) write cycle 2 ( 1,4,8 ) (/cs controlled) notes: 1. a write occurs during the overlap of a low /we, a low /cs1 and low /ub and/or /lb. 2. twr is measured from the earlier of /cs, /lb, /ub, or / we going high to the end of write cycle. 3. during this period, i/o pins are in the output state so that the input signals of opposite phase to the output must not be applied. 4. if the /cs, /lb and /ub low transition occur simultaneously with the /we low transition or after the /we transition, outputs remain in a high impedance state. 5 . q(data out) is the same phase with the write data of this write cycle. 6. q(data out) is the read data of the next address. 7. transition is measured +200mv from steady state. this parameter is sampled and not 100% tested. 8 . /cs in high for the standby, low for active /ub and /lb in high for the standby, low for active data vali d addr data out / cs / ub , / lb / we twc tcw twr (2) tbw taw twp data in high - z tas twhz (3, 7 ) tdw tdh tow ( 5 ) ( 6 ) data valid addr data out / cs / ub , / lb / we twc tcw twr (2) tbw taw twp data in tdw tdh high - z high - z tas
HY62UF16201A series rev.0 7 / aug . 2001 7 data retention electric characteristic t a =0 c to 70 c/ - 40 c to 85 c ( i ),unle ss otherwise specified symbol parameter test condition min . typ . max . unit v dr vcc for data retention /cs > vcc - 0.2v or /ub = /lb > vcc - 0.2v, 1. 2 - 3.3 v v in > vcc - 0.2v or v in < vss + 0.2v i ccdr data retention current vcc=1.5v, /cs > vcc - 0 .2v or /ub = /lb > vcc - 0.2v, ll - - 10 ua v in > vcc - 0.2v or sl - - 2 ua v in < vss + 0.2v t cdr chip deselect to data retention time see data retention timing diagram 0 - - ns t r operating recovery time trc ( 3 ) - - ns notes: 1. typical value s are under the condition of t a = 25 c . 2. typical values are sampled and not 100% tested 3 . trc is read cycle time. data retention timing diagram cs vdr cs > vcc-0.2v tcdr tr vss vcc 2.7v data retention mode or /ub &/lb or /ub = /lb > vcc ? 0.2v
HY62UF16201A series rev.0 7 / aug . 2001 8 package information 48ball fine pitch bal l grid array package( f ) bottom view top view b a a1 corner b1/2 index area 6 5 4 3 2 1 a a b c d c c1 e f g c1/2 c1/2 h b1/2 b1 side view 5 e1 e2 c e seating plane 4 a r 3 d(diameter) [ HY62UF16201Af ] [ HY62UF16201Af1 ] symbol min. typ. max. min. typ. max. a - 0.75 - - 0.75 - b - 3.75 - - 3.75 - b1 6.90 7.00 7.10 5.90 6.00 6.10 c - 5.25 - - 5.25 - c1 7.90 8.00 8.10 7.90 8.00 8.10 d 0.3 0.35 0.4 0.3 0.35 0.4 e - - 1.10 - 1.0 1.10 e1 0.75 0.80 0.85 - 0.75 - e2 0.17 - - 0.2 0.25 0.3 r - - 0.12 - - 0.08 note 1. dimensioning and tolerancing per asme y14. 5 m - 1994. 2. all dimensions are millimeters. 3. dimension ?d? is measured at the maximum solder ball diameter in a plane paralle l to datum c. 4. primary datum c(seating plane) is defined by the crown of the solder balls. 5 . this is a controlling dimension.
HY62UF16201A series rev.0 7 / aug . 2001 9 marking instruction [ HY62UF16201A f ] package marking example h y u f 6 2 1 a c s s t y y w w p x x x x x k o r fbga (7mm x 8mm) index ? hyuf621ac : part name c : power consumption - l : low low power - s : super low power ? ss : speed - 55 : 55ns - 70 : 70ns - 85 : 85ns - 10 : 100ns ? t : temperature - c : industrial ( - 0 ~ 70 c ) - i : industrial ( - 40 ~ 85 c ) ? yy : year (ex : 00 = year 2000, 01= year 2001) ? ww : work week ( ex : 12 = work week 12 ) ? p : process code : a(7.0mm x 8.0mm) ? xxxxx : lot no. ? kor : origin country note - capital letter : fixed item - small letter : non - fixed item package marking example h y u f 6 2 1 a c s s t y y w w p x x x x x k o r fbga (7mm x 8mm) index ? hyuf621ac : part name c : power consumption - l : low low power - s : super low power ? ss : speed - 55 : 55ns - 70 : 70ns - 85 : 85ns - 10 : 100ns ? t : temperature - c : industrial ( - 0 ~ 70 c ) - i : industrial ( - 40 ~ 85 c ) ? yy : year (ex : 00 = year 2000, 01= year 2001) ? ww : work week ( ex : 12 = work week 12 ) ? p : process code : a(7.0mm x 8.0mm) ? xxxxx : lot no. ? kor : origin country note - capital letter : fixed item - small letter : non - fixed item
HY62UF16201A series rev.0 7 / aug . 2001 10 [ HY62UF16201Af1 ] package marking example h y u f 6 2 1 a c s s t y y w w p x x x x x k o r fbga (6mm x 8mm) index ? hyuf621ac : part name c : power consumption - l : low low power - s : super low power ? ss : speed - 55 : 55ns - 70 : 70ns - 85 : 85ns - 10 : 100ns ? t : temperature - c : industrial ( - 0 ~ 70 c ) - i : industrial ( - 40 ~ 85 c ) ? yy : year (ex : 01 = year 2001, 02= year 2002) ? ww : work week ( ex : 12 = work week 12 ) ? p : process code : b(6.0mm x 8.0mm) ? xxxxx : lot no. ? kor : origin country note - capital letter : fixed item - small letter : non - fixed item package marking example h y u f 6 2 1 a c s s t y y w w p x x x x x k o r fbga (6mm x 8mm) index ? hyuf621ac : part name c : power consumption - l : low low power - s : super low power ? ss : speed - 55 : 55ns - 70 : 70ns - 85 : 85ns - 10 : 100ns ? t : temperature - c : industrial ( - 0 ~ 70 c ) - i : industrial ( - 40 ~ 85 c ) ? yy : year (ex : 01 = year 2001, 02= year 2002) ? ww : work week ( ex : 12 = work week 12 ) ? p : process code : b(6.0mm x 8.0mm) ? xxxxx : lot no. ? kor : origin country note - capital letter : fixed item - small letter : non - fixed item

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